The present invention relates generally to synchronous DC-to-DC boost converters operating in pulse-frequency modulation (PFM) mode, and more particularly to implementations including improvements which avoid undesired transfer of charge back into an input signal source when the direction of the inductor current reverses, and which also avoid the need for use of a costly, high-speed, high precision comparator to accomplish suitably fast, accurate operation.
FIG. 1A shows a basic prior art DC-to-DC boost converter 1A. In a synchronous DC-to-DC boost converter the output voltage Vout is generally greater than the input voltage Vin. In boost converter 1A, N-channel power switch transistor 3 is turned on to build up the current IL flowing through an inductor L to a conductor 4 which is connected to the drain of power switch transistor 3 and also to the anode of a rectifier diode switch 6. The rising slopes of inductor current IL in FIG, 1B show this build up of IL while power switch transistor 3 is on. When power switch transistor 3 is turned off, the inductor current IL continues to flow, and passes in the forward direction through diode 6 and delivers charge through Vout conductor 7 to an external load 15, a capacitor C and series-connected resistors R1 and R2. The falling slopes of the IL waveform in FIG. 1B show the decay of inductor current IL. The output voltage Vout on conductor 7 is divided by resistor divider R1/R2 to produce a feedback voltage VFB on conductor 9 which is connected to one input of a control loop circuit 2. Another input of control loop circuit 2 is connected to a reference voltage Vref with which the feedback voltage VFB is to be compared. Control loop circuit 2 operates to control the switching of power switch transistor 3 so as to regulate Vout to a constant value which is equal to Vref×(R1+R2)/R2. Capacitor C supplies current to the load 15 during the phase when inductor L is not delivering inductor current IL to the overall load including load device 15, capacitor C, and voltage divider R1/R2, and also performs the function of reducing ripple in Vout.
An advantage of DC-to-DC boost converter 1A is that under light load conditions as indicated by curve B in FIG. 1B, inductor current IL will eventually decay only to zero, but no lower because diode 6 can only conduct current in its forward direction. Consequently, problems associated with a reverse flow of inductor current to the input voltage source circuit, as described in the following paragraph, are avoided. However, since efficiency is at the core of DC-to-DC boost converter design, the circuit structure shown in FIG. 1A is not well-suited for low voltage designs because the typical several hundred millivolt voltage drop across diode 6 tends to substantially diminish the overall efficiency, especially in applications in which Vin and Vout both have very low values.
Synchronous DC-to-DC boost converter designs with relatively low values of Vin and Vout generally utilize a “synchronous rectifier” P-channel power transistor 11 as shown in synchronous DC-to-DC boost converter 1B of FIG. 2A rather than a rectifier diode 6 as in FIG. 1A. Since the “on” resistance of P-channel “synchronous rectifier” switching transistor 11 is designed to be very small, the voltage drop across it is significantly lower than the voltage drop across diode 6 in FIG. 1A. This reduces the converter power loss of the boost converter. The circuit structure of FIG. 2A therefore is better suited for low voltage applications than the circuit structure of FIG. 1A. The control signals applied to the gates of N-channel transistor 3 and P-channel synchronous rectifier transistor 11 in FIG. 2A typically are non-overlapping in order to prevent “shoot-through” currents between Vout and ground. When N-channel transistor 3 is turned on it operates to build up the current IL in inductor L as indicated by the rising slopes of the waveforms of inductor current IL in FIG. 2B. When transistor 3 is turned off and P-channel output power transistor 11 is turned on it delivers the ramp up are built up inductor current IL to the total load including capacitor C, voltage divider R1,R2, and external load 15, as generally indicated by the falling slopes of the IL waveforms in FIG. 2B. Note that curve B for inductor current IL under light load conditions in FIG. 2B indicates that the inductor current IL can ramp down to negative values (i.e., undergo a direction reversal) in a synchronous DC-to-DC boost rectifier which does not have any means for preventing reverse inductor flow.
Unlike diode 6 in FIG. 1A, the P-channel output power transistor 11 in FIG. 2A can allow current flow through it in both directions. Therefore, if the direction of inductor current IL is reversed (which can happen when the load current demand is low or when the switching cycle of output power transistor 11 is of long duration), the current can flow back from Vout through conductor 7 and inductor L to Vin. This is undesirable since it increases the power loss in the boost converter and also because the input voltage source circuit (not shown) which supplies Vin may not be able to handle such “backflow” current.
In order to avoid undesired transfer of charge back from Vout to Vin and into an input signal source, it is necessary to synchronously turn off P-channel transistor 11 just as the inductor current IL begins to reverse direction, to thereby emulate the function of rectifying diode 6 in Prior Art FIG. 1A without incurring the power loss of diode 6. Referring to synchronous DC-to-DC converter IC in FIG. 3, a typical technique is to provide a switch control circuit 20A which is able to detect if the direction of the inductor current IL flowing through output power transistor 11 is reversed, and if so, then turn off output power transistor 11. Switch control circuit 20A includes a comparator 12 connected to monitor the voltage between the drain and source of P-channel power output transistor 11. An output of comparator 12 is logically OR'ed with an output 8B of control loop circuit 2 to control output power transistor 11 in synchronization with the output 8A which controls N-channel power transistor 3. When the direction of the inductor current IL is reversed, that raises the voltage Vout on the source of output power transistor 11 slightly above its drain voltage. Comparator 12 senses the change of direction of inductor current IL and terminates the “on” cycle (see, for example, FIG. 5) of the power output transistor 11.
However, the foregoing technique requires that comparator 12 have a very small input offset voltage and a very fast response time. As IL starts reversing direction, inductor current IL continues to build up (i.e., ramp up) in the reverse direction. If comparator 12 has zero input offset voltage it will change state as soon as it has a positive input voltage as the result of reversal of inductor current IL through power output transistor 11. P-channel power output transistor 11 is generally designed to be very large in size and therefore has a very small impedance, for example one fourth of an ohm. Consequently, the voltage produced by the relatively small reverse inductor current flowing through the relatively small impedance of power output transistor 11 may be “overwhelmed” by the input offset voltage of comparator 12. If comparator 12 has a positive offset voltage, that means inductor current IL has to build up to a relatively large negative value to trigger comparator 12, causing it to switch too late, which is undesirable because from the standpoint of power efficiency. In the opposite case, if comparator 12 has a large negative input offset voltage, comparator 12 will be prematurely triggered and change state too soon, which also results in undesired power loss. (A typical CMOS comparator may have an input offset voltage of, for example, +−5 millivolts, which means that in the configuration of FIG. 3 there may be as much as 20 milliamperes of reverse inductor current IL) Also, the response time of comparator 12 may delay the “off” time of switching transistor 11, which shifts the timing of the turn-off of power output transistor 11 further away from the exact instant at which the direction of inductor current IL is reversed.
Therefore, the comparator 12 of boost converter 1C of FIG. 3 generally needs to be precise, meaning that it needs to have a low input offset voltage, and also needs to be fast, meaning that it needs to have a very short delay time, to prevent unnecessary power loss. However, implementation of such a comparator is generally costly because fast response time or low delay usually necessitates use of circuit implementations that require increased power consumption, and because achieving low input offset voltages often necessitates use of complex, expensive circuit techniques, such as auto-zeroing circuitry.
There is an unmet need for a very accurate synchronous DC-to-DC boost converter which avoids transfer of charge back into an input signal source when the direction of the inductor current changes.
There also is an unmet need for a very accurate synchronous DC-to-DC boost converter that can detect a and prevent reversed inductor current without requiring the use of an expensive, fast, precise comparator.